Strain engineering can result in increased performance in semiconductor devices, such as, for example, complementary metal-oxide semiconductor (CMOS) devices. Tensile strain is beneficial for n-type field-effect transistors (NFETs) and compressive strain is beneficial for p-type field-effect transistors (PFETs).
Conventional external strain techniques, such as embedded source/drain regions, and stress liners, have limited effect in some devices, such as fin field-effect transistors (FinFETs), due to the highly scaled pitches and the three-dimensional (3D) nature of a FinFET. Channel strain remains one of few options that continue to provide performance benefits regardless of pitches and device architectures.
Accordingly, there is a need for improved techniques for forming tensile and compressively strained channel regions for NFET and PFET devices.